The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for forming a bit line and a storage node contact through the use of a damascene process.
Hereinafter, with reference to FIGS. 1A to 1D, there are provided descriptions on problems arose by a conventional method for forming a contact hole.
Referring to FIG. 1A, a first inter-layer insulation layer 13 is formed on a substrate 11 providing various elements for constructing a semiconductor device such as a word line (not shown), an impurity contact region 12 and so forth. The first inter-layer insulation layer 13 is also called as a word line insulation layer. The first inter-layer insulation layer 13 is selectively etched to form a contact hole exposing the impurity contact region 12.
Next, a plurality of plugs 14 for storage node contacts or bit line contacts are formed. The plug 14 is formed in the contact hole and is contacted to the exposed impurity contact region 12.
It is general to use polysilicon for the plug 14. However, instead of the polysilicon, a multi-layered structure stacked of a tungsten layer and a barrier metal layer including Ti/TiN typically used in a diffusion barrier layer is recently used for the plug 14.
After the plug 14 formation, a diffusion barrier layer 15 having the typical structure of Ti/TiN structure is formed on the plug 14 in order to prevent a source gas used in a deposition of a bit line metal layer 16 from reacting with the plug 14 and the impurity contact region 12. Then, on an upper surface of the diffusion barrier layer 15, the bit line metal layer 16 is formed by using such materials as polysilicon, tungsten and so forth or metal alloys such as tungsten nitride, tungsten silicide and so forth.
Next, a plasma enhanced chemical vapor deposition (PECVD) technique or a low pressure chemical vapor deposition (LPCVD) technique is performed to form a hard mask nitride layer 17. Herein, the hard mask nitride layer 17 is made of nitride-based materials including silicon oxynitride or silicon nitride.
As shown, it is also possible to additionally form a buffer layer using undoped silicate glass (USG) in order to reduce stress generated between the bit line metal layer 16 and the hard mask nitride layer 17.
Referring to FIG. 1B, the hard mask nitride layer 17, the bit line metal layer 16 and the diffusion barrier layer 15 are selectively etched through the use of a bit line etch mask to thereby form a bit line.
The high level of integration in a semiconductor device makes it difficult to stably secure a pattern formation process margin and overlay accuracy. Thus, a self-align contact (SAC) process is adopted to solve the above problems because it uses pre-deposited materials instead of an additional mask during an etch process for forming various patterns such as a contact hole pattern. As a result of this approach, the SAC process is capable of reducing costs for a semiconductor device fabrication process. Among various etch methods of the SAC process, a nitride layer is typically used as an etch stop layer.
Therefore, during the SAC process, an insulation layer is etched under conditions that the nitride layer encompasses an upper part and lateral walls of a conductive pattern such as a gate electrode or a bit line and an oxide layer is subsequently etched in a higher rate than the nitride layer.
Since the SAC process is applied to a storage node contact formation process, a nitride-based etch stop layer 18 is deposited on the above entire structure including the bit line in order to prevent a bit line loss during the SAC process. FIG. 1C is a cross-sectional view showing an etch profile of the etch stop layer 18 formed along an upper part and lateral walls of the bit line.
With reference to FIG. 1D, a second inter-layer insulation layer 19 is formed on top of the etch stop layer 18. The second inter-layer insulation layer is called bit line insulation layer. At this time, the bit line insulation layer 19 is commonly made of USG.
Next, under a target that the second inter-layer insulation layer 19 remains in a predetermined thickness on the etch stop layer 18, a chemical mechanical polishing process (CMP) is performed to planarize the second inter-layer insulation layer 19. After the CMP process, a photoresist pattern 20 for forming a storage node contact, and the second inter-layer insulation layer 19 and the etch stop layer 18 are sequentially etched by using the photoresist pattern 20 as an etch mask. This process is the SAC process. From this SAC process, a contact hole 21 exposing a surface of the plug 14 allocated between the bit lines is formed. As shown in FIG. 1D, the etch stop layer 18 is etched during the SAC process and remains as a spacer at lateral sides of the diffusion barrier layer 15, the bit line metal layer 16 and the hard mask nitride layer 17.
Prior to forming the contact hole 21, an additional process for forming a contact pad is generally performed to improve an overlap margin. However, descriptions on this additional process are omitted.
Meanwhile, because of the high integration of the semiconductor device, such a unit element as a word line, a bit line or so forth is arrayed vertically, and a contact pad is introduced. However, a width of the bottom structure gets narrower. As a result, an aspect ratio progressively increases. For instance, in case that the aspect ratio is above about 3, a gap-fill property is diminished. Particularly, a void is generated in the course of filling-up a space between the bit lines when the second inter-layer insulation layer 19 is deposited.
Accordingly, during the SAC process for forming the contact hole 21, the hard mask nitride layer 17 is attacked by this etching. This attacked portion is denoted as the reference numeral 22 in FIG. 1D. Also, there is a problem in an insulation property between the bit line metal layer 16 and a subsequent storage node. Furthermore, an overall electrical property is deteriorated.
It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device with use of damascene process in order to prevent a conductive pattern from being attacked during a storage node contact hole formation process.
In accordance with an aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: forming a bit line insulation layer on a substrate structure having a plurality of plugs; forming a group of trenches exposing a group of the plugs by etching the bit line insulation layer; burying each trench by a conductive material to form a bit line electrically connected to the exposed plug; isolating the bit line by performing a chemical mechanical polishing process until the bit line insulation layer is exposed; forming an inter-layer insulation layer on the above structure including the bit line; and etching selectively the inter-layer insulation layer and the bit line insulation layer to form storage node contact holes exposing another group of the plugs.